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19-0554; Rev 0; 5/06
Complete VGA 1:2 or 2:1 Multiplexer
General Description
The MAX4885 integrates high-bandwidth analog switches and level-translating buffers to implement a complete 1:2 or 2:1 multiplexer for VGA signals. The device provides switching for RGB, display data channel (DDC), and horizontal and vertical synchronization (HSYNC, VSYNC) signals. A low-noise charge pump with internal capacitors provides a boosted gate-drive voltage to improve performance of the RGB switches. In the 1:2 multiplexer mode, HSYNC/VSYNC inputs feature level-shifting buffers to support low-voltage CMOS or standard TTL-compatible graphics controllers. In the 2:1 multiplexer mode, the output buffers for the HSYNC/VSYNC inputs are disabled, allowing bidirectional signaling. In both modes, DDC signals are voltage-clamped to an external voltage to provide level translation and protection. The MAX4885 features a 5A shutdown mode and is ESD protected to 8kV Human Body Model (HBM) on externally routed pins. The MAX4885 is specified over the extended (-40C to +85C) temperature range, and is available in the 32pin, 5mm x 5mm TQFN package. +5V Single-Supply Operation Programmable Voltage Clamp for Open-Drain DDC Signals Low 5 (typ) On-Resistance (R, G, B Signals) Low 13pF (typ) On-Capacitance (R, G, B Signals) Break-Before-Make Switching Protects Against Circuit Shorts 8kV HBM ESD Protection on Externally Routed Pins Low 300A Supply Current (Lower than 1A with Charge Pump Disabled) Space-Saving, Lead-Free, 32-Pin (5mm x 5mm) TQFN Package
Features
MAX4885
Ordering Information
PART MAX4885ETJ+ TEMP RANGE PIN-PACKAGE PKG CODE T3255-4
Applications
Notebook Computers Digital Projectors Computer Monitors Servers KVM Switches
-40C to +85C 32 TQFN-EP*
*EP = Exposed pad. +Denotes lead-free package.
Pin Configuration
H1 H2 V1 B1 V+ V2 B2
Typical Operating Circuit
TOP VIEW
24 G1 25 R1 26 DDCB1 27 DDCA1 28 GND 29 V+ 30 M 31 SEL 32 1 QP
23
22
21
20
GND
19
18
17 16 15 14 13 G2 R2 DDCB2 DDCA2 GND V+ VCL EN
+3.3V +5V 0.1F VCL 3 GRAPHICS CONTROLLER 2 DOCKING STATION 2 V+ 0.1F
MAX4885
R0, B0, G0 H0, V0 DDCA0, DDCB0 SEL M EN R1, G1, B1 H1, V1 DDCA1, DDCB1 R2, G2, B2 H2, V2 DDCA2, DDCB2 GND 3 2 2 3 2 2 VGA PORT 2 VGA PORT 1
MAX4885
12 11
*EP
10 9
2 R0
3 G0
4 B0
5 H0
6 V0
7 DDCA0
8 DDCB0
TQFN
*EXPOSED PADDLE CONNECTED TO GND
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Complete VGA 1:2 or 2:1 Multiplexer MAX4885
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) V+, VCL .....................................................................-0.3V to +6V R_, G_, B_, DDCA_, DDCB_, SEL, M, EN, QP (Note 1) ...........................................-0.3V to V+ + 0.3V H_, V_ .......................................................................-0.3V to +6V Continuous Current Through RGB Switches ....................70mA Continuous Current Through HV, DDC Switches.............50mA Peak Current Through RGB Switches (pulsed at 1ms, 10% duty cycle).................................140mA Peak Current Through HV, DDC Switches (pulsed at 1ms, 10% duty cycle)..............................................................100mA Continuous Power Dissipation (TA = +70C) 32-Pin TQFN (derate 21.3mW/C above +70C) ........1702mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: Signals exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +5.0V 10%, VCL = +3.3V 10%, TA = TMIN to TMAX, QP = GND, unless otherwise noted. Typical values are at V+ = +5.0V, VCL = +3.3V and TA = +25C.)
PARAMETER Supply Voltage Range Clamp Voltage Range V+ Quiescent Supply Current VCL Quiescent Supply Current V+ Shutdown Current VCL Shutdown Current RGB ANALOG SWITCHES On-Resistance On-Resistance Matching On-Resistance Flatness Off-Leakage Current On-Leakage Current Charge Injection HV MULTIPLEXER Input-Voltage Low Input-Voltage High High-Output Drive Current Low-Output Drive Current On-Resistance Charge Injection VILHV VIHHV IOHHV IOLHV RONHV Q M = GND M = GND VOUT = V+ - 0.5V, M = GND VOUT = +0.5V, M = GND H_ = V_ = +2.5V, IIN = -40mA, M = V+ H_, V_ = 0V, M = V+, CL = 1000pF 21 2.0 -16 +16 15 0.8 V V mA mA pC RON RON RFLAT(ON) IL(OFF) IL(ON) Q 0V < VIN < +2.5V, IIN = -40mA QP = GND QP = V+ 5 6 0.5 0.02 -1 -1 10 8 7.5 10 1.5 0.75 +1 +1 A A pC SYMBOL V+ VCL I+ ICL I+SHDN ICLSHDN V+ = +5.5V VCL = V+ = +5.5V V+ = +5.5V, all digital inputs to V+ or GND VCL = V+ = +5.5V, all digital inputs to V+ or GND QP = GND QP = V+ CONDITIONS MIN 4.5 2.7 0.3 TYP MAX 5.5 V+ 0.5 1 1 5 1 UNITS V V mA A A A A
0V < VIN < +2.5V, IIN = -40mA 0V < VIN < +2.5V, IIN = -40mA R_, G_, B_ = 0V or +5.5V, EN = GND R_, G_, B_ = 0V or +5.5V, EN = V+ R_, G_, B_ = 0V, CL = 1000pF QP = GND QP = V+
2
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Complete VGA 1:2 or 2:1 Multiplexer
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5.0V 10%, VCL = +3.3V 10%, TA = TMIN to TMAX, QP = GND, unless otherwise noted. Typical values are at V+ = +5.0V, VCL = +3.3V and TA = +25C.)
PARAMETER DDC MULTIPLEXER On-Resistance DDC Leakage Charge Injection SWITCH LOGIC (SEL, M, EN, QP) Input-Low Voltage Input-High Voltage Input Leakage Current ESD PROTECTION Human Body Model, all pins ESD Protection Human Body Model, R_, G_, B_, H_, V_, DDCA_, DDCB_ 2 8 kV kV VIL VIH ILEAK V+ = +5.5V V+ = +4.5V VIN = V+ 2.0 -1 +1 0.8 V V A RON(DDC) IL(DDC) Q VIN < +0.4V, VCL = +3.0V, IIN = -20mA VCL - 0.4V < VOUT < VCL, VIN = V+ DDCA_, DDCB_ = 0V, CL = 1000pF -1 10 20 +1 A pC SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX4885
AC ELECTRICAL CHARACTERISTICS
(V+ = +5.0V 10%, VCL = +3.3V 10%, TA = TMIN to TMAX, QP = GND. Typical values are at V+ = +5.0V, VCL = +3.3V and TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Bandwidth Insertion Loss Crosstalk Off-Capacitance On-Capacitance Charge-Pump Noise SYMBOL fMAX ILOS VCT COFF CON VNQP RS = RL = 50 1MHz < f < 50MHz, RS = RL = 50 1MHz < f < 50MHz, VIN = 0.7VP-P, RS = RL = 50 f = 1MHz, QP = GND or V+ f = 1 MHz VIN = +1.0V, RS = RL = 50 QP = GND QP = V+ CONDITIONS QP = GND QP = V+ QP = GND QP = V+ MIN TYP 350 350 0.85 1 -40 5 13 17 50 200 1.2 1.6 MAX UNITS MHz dB dB pF pF V
_______________________________________________________________________________________
3
Complete VGA 1:2 or 2:1 Multiplexer MAX4885
TIMING CHARACTERISTICS
(V+ = +5.0V 10%, VCL = +3.3V 10%, TA = TMIN to TMAX, QP = GND. Typical values are at V+ = +5.0V, VCL = +3.3V and TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Charge-Pump Startup Time RGB ANALOG SWITCHES Turn-On Time Turn-Off Time Propagation Delay Output Skew Between Ports HV MULTIPLEXER Turn-On Time Turn-Off Time Propagation Delay DDC MULTIPLEXER Turn-On Time Turn-Off Time Propagation Delay tON tOFF tPD VIN = +1.0V, RL = 100, Figure 1 VIN = +1.0V, RL = 100, Figure 1 CL = 10pF, Figure 2 0.1 0.25 5 s s ns tON tOFF tPD M = 0, Figure 1 M = 0, Figure 1 CL = 10pF M = GND M = V+ 0.1 6 0.1 16 5 s s ns tON tOFF tPD tSKEW VIN = +1.0V, RL = 100, Figure 1 VIN = +1.0V, RL = 100, Figure 1 CL = 10pF, Figure 2, RL = RS = 50 CL = 10pF, Skew between any two ports: R, G, B. Figure 2, RS = RL = 50 0.1 0.1 30 7 s s ns ps SYMBOL tQPON CONDITIONS MIN TYP 150 MAX UNITS s
Note 2: Timing parameters are guaranteed by design and correlation over the full operating temperature range.
Typical Operating Characteristics
(V+ = +5.0V, VCL = +3.3V and TA = +25C, unless otherwise noted.)
RON vs. VR0* (RGB SWITCHES)
MAX4885 toc01
RON vs. VR0* (RGB SWITCHES)
QP = 0 OR 1 QP = 1 30 25 RON () 20 15 10 TA = +85C TA = +25C RON ()
MAX4885 toc02
RON vs. VR0* (HV SWITCHES)
MAX4885 toc03
10 9 8 7 RON () 6 5 4 3 2 1 0 0 1 2 VR0 (V) *R0, G0, B0 ARE INTERCHANGEABLE. 3 4 5 TA = -40C TA = +25C TA = +85C
35
12 10 8 6 4 2 TA = +85C TA = +25C TA = -40C
5 0 0 1 2 VR0 (V) *R0, G0, B0 ARE INTERCHANGEABLE. TA = -40C 3 4
0 0 1 2 VR0 (V) *R0, G0, B0 ARE INTERCHANGEABLE. 3 4 5
4
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Complete VGA 1:2 or 2:1 Multiplexer MAX4885
Typical Operating Characteristics (continued)
(V+ = +5.0V, VCL = +3.3V and TA = +25C, unless otherwise noted.)
RON vs. VDDAC0* (DDC SWITCHES)
MAX4885 toc04
HV BUFFER OUTPUT VOLTAGE HIGH vs. TEMPERATURE
MAX4885 toc05
HV BUFFER OUTPUT VOLTAGE LOW vs. TEMPERATURE
1.8 OUTPUT VOLTAGE LOW (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 I = 16mA
MAX4885 toc06
75
5.0 4.8 OUTPUT VOLTAGE HIGH (V) 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2
I = 16mA
2.0
60
RON ()
45
VCL = +3.3V TA = +85C TA = +25C TA = -40C
VCL = +5.0V TA = +85C TA = +25C TA = -40C
30
15
0 0 0.5 1.0 1.5 2.0 2.5 3.0 VDDAC0 (V) *DDAC0 AND DDCB0 ARE INTERCHANGEABLE.
3.0 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
RGB LEAKAGE CURRENT vs. TEMPERATURE
0.9 0.8 LEAKAGE CURRENT (nA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 -15 10 35 60 85 TEMPERATURE (C) ON LEAKAGE 0.5 OFF LEAKAGE 0 -40 QP = 0
MAX4885 toc07
HV LEAKAGE CURRENT vs TEMPERATURE
MAX4885 toc08
DDC LEAKAGE CURRENT vs. TEMPERATURE
0.9 0.8 LEAKAGE CURRENT (nA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ON LEAKAGE OFF LEAKAGE -40 -15 10 35 60 85
MAX4885 toc09
1.0
3.0 2.5 LEAKAGE CURRENT (nA) 2.0 1.5 ON LEAKAGE 1.0 OFF LEAKAGE
1.0
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
RGB CHARGE INJECTION vs. COM VOLTAGE
MAX4885 toc10
SUPPLY CURRENT vs. TEMPERATURE
MAX4885 toc11
tON vs. TEMPERATURE (RGB SWITCHES)
QP = 0
MAX4885 toc12
15
0.50 0.45 0.40 SUPPLY CURRENT (mA) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0
6.0 5.0 TURN-ON TIME (s) QP = 0 4.0 3.0 QP = 1 2.0 1.0 0
12 CHARGE INJECTION (pC)
9
6 QP = 1 QP = 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VCOM (V)
3
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
_______________________________________________________________________________________
5
Complete VGA 1:2 or 2:1 Multiplexer MAX4885
Typical Operating Characteristics (continued)
(V+ = +5.0V, VCL = +3.3V and TA = +25C, unless otherwise noted.)
tON vs. TEMPERATURE (HV, DDC SWITCHES)
MAX4885 toc13
tOFF vs. TEMPERATURE (RGB SWITCHES)
MAX4885 toc14
tOFF vs. TEMPERATURE (HV, DDC SWITCHES)
MAX4885 toc15
3.0 2.5 TURN-ON TIME (s) 2.0 1.5 1.0 0.5 0 -40 -15 10 35 60
150 125 TURN-OFF TIME (ns) 100 75 50 25 0 QP = 0 QP = 1
30 25 TURN-OFF TIME (ns) 20 DDC 15 10 5 0 HV
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
RGB PROPAGATION DELAY vs. TEMPERATURE
MAX4885 toc16
ON-RESPONSE vs. FREQUENCY
MAX4885 toc17
CROSSTALK vs. FREQUENCY
QP = 0 OR 1 -10 -20 CROSSTALK (dB) -30 -40 -50 -60 -70
MAX4885 toc18
1000
0 -1 QP = 1 ON-RESPONSE (dB) -2 -3 -4 -5 -6 0 100 200 FREQUENCY (MHz) 300 QP = 0
0
PROPAGATION DELAY (ps)
800
600 tPHL 400 tPLH
200
-80 -90 400 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
OFF-ISOLATION vs. FREQUENCY
-10 -20 OFF-ISOLATION (dB) -30 -40 -50 -60 -70 -80 -90 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) QP = 0 OR 1
MAX4885 toc19
0
6
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Complete VGA 1:2 or 2:1 Multiplexer
Timing Circuits/Timing Diagrams
MAX4885
V+ V+ R0, G0, B0 LOGIC INPUT VOUT RL SEL LOGIC INPUT GND SWITCH OUTPUT 0V CL VOUT 0.9 x V0UT t OFF 0.9 x VOUT V+ 0V 50% t r < 5ns t f < 5ns 50%
MAX4885
VN_
R1, G1, B1 R2, G2, B2
t ON
VOUT = VN_
CL INCLUDES FIXTURE AND STRAY CAPACITANCE. RL RL + RON
(
)
IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 1. Switching Time
1V 50% INPUT 50% 0V tPLH tPHL
RS = RL = 50 CL = 10pF
VOH
0.9V 50% OUTPUT tSKEW = | tPLH - tPHL | tPD = MAX (tPLH, tPHL) 50% 0V
Figure 2. Propagation Delay and Skew Waveforms
MAX4885
V+ VOUT V+ VOUT RGEN R1, G1, B1 R2, G2, B2 GND R0, G0, B0 CL SEL OFF ON Q = (V OUT )(C L ) LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. OFF VOUT IN OFF ON OFF
V GEN
VIL TO VIH
IN
Figure 3. Charge Injection _______________________________________________________________________________________ 7
Complete VGA 1:2 or 2:1 Multiplexer MAX4885
Timing Circuits/Timing Diagrams (continued)
+5V 10nF NETWORK ANALYZER 0V OR V+ SEL V+ R0, G0, B0 VIN 50 50 V OFF-ISOLATION = 20log OUT VIN ON-LOSS = 20log VOUT VIN
MAX4885
R1, G1, B1 50 R2, G2, B2 GND VOUT MEAS REF
V CROSSTALK = 20log OUT VIN
50
50
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN R0 AND R1 OR R2 ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN R0 AND R1 OR R2 ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 4. On-Loss, Off-Isolation, and Crosstalk
Pin Description
PIN 1 2 3 4 5 6 7 8 9 NAME QP R0 G0 B0 H0 V0 DDCA0 DDCB0 EN FUNCTION Charge-Pump Enable, Active Low. Drive QP low for normal operation. Drive QP high to disable the internal charge pump. RGB Analog I/O RGB Analog I/O RGB Analog I/O Horizontal Sync I/O Vertical Sync I/O DDC I/O DDC I/O Enable Input, Active Low. Drive EN low for normal operation. Drive EN high to disable the device. All I/Os are high-impedance and charge pump is off when the device is disabled. DDC Clamp Voltage. Open-drain DDCA_ and DDCB_ outputs are clamped to one diode-drop below VCL. +2.7V < VCL < V+. Connect VCL to +3.3V for voltage clamping, or connect to V+ to disable clamping. Bypass VCL to GND with a 0.1F or larger ceramic capacitor. Supply Voltage. V+ = +5.0V 10%. Bypass each to GND with a 0.1F or larger ceramic capacitor. Ground DDC I/O DDC I/O RGB Analog I/O RGB Analog I/O RGB Analog I/O
10 11, 21, 30 12, 20, 29 13 14 15 16 17
VCL V+ GND DDCA2 DDCB2 R2 G2 B2
8
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Complete VGA 1:2 or 2:1 Multiplexer
Pin Description (continued)
PIN 18 19 22 23 24 25 26 27 28 31 32 EP NAME H2 V2 V1 H1 B1 G1 R1 DDCB1 DDCA1 M SEL EP Horizontal Sync I/O Vertical Sync I/O Vertical Sync I/O Horizontal Sync I/O RGB Analog I/O RGB Analog I/O RGB Analog I/O DDC I/O DDC I/O Mode Select. Drive M low for 1:2 multiplexer mode. Drive M high for 2:1 multiplexer mode. See Tables 1, 2, and 3. Select. Logic input for switching RGB, HV, and DDC switches. See Tables 1, 2, and 3. Exposed Pad. Connect exposed pad to ground. FUNCTION
MAX4885
Detailed Description
The MAX4885 integrates high-bandwidth analog switches and level-translating buffers to implement a complete 1:2 or 2:1 multiplexer for VGA signals. The device provides switching for RGB, HSYNC, VSYNC, and DDC signals. A low-noise charge pump with internal capacitors provides a boosted gate-drive voltage to improve performance of the RGB switches. The device provides two modes of operation: 1:2 and 2:1. In 1:2 mode (M = 0), the HSYNC and VSYNC inputs feature level-shifting buffers to support TTL output logic levels from low-voltage graphics controllers. These buffered switches may be driven from as little as +2.0V up to +5.5V. In 2:1 mode (M=1), the output buffers for the HSYNC and VSYNC signals are disabled. In both modes, RGB signals are routed with the same high-performance analog switches, and DDC signals are voltage clamped to a diode drop less than VCL. Voltage clamping provides protection and compatibility with DDC signals and low-voltage ASICs. In keyboard/video/mouse (KVM) applications, VCL is normally set to +5V because low-voltage clamping is not required, as specified by the VESA standard. Drive EN logic high to shut down the MAX4885. In shutdown mode, supply current is reduced to 5A and all switches are high impedance, providing high-signal rejection. The RGB, HSYNC, VSYNC, and DDC switches are ESD protected to 8kV by the Human Body Model.
Table 1. RGB Truth Table
EN 0 SEL 0 R0 to R1 G0 to G1 B0 to B1 R0 to R2 G0 to G2 B0 to B2 R_, B_, and G_, High Impedance FUNCTION
0 1
1 X
X = Don't Care
RGB Switches
The MAX4885 provides three SPDT high-bandwidth switches to route standard VGA R, G, and B signals (see Table 1). A boosted gate-drive voltage is generated by an internal charge pump to improve performance of the RGB switches. The R, G, and B analog switches are identical, and any of the three switches can be used to route red, green, or blue video signals. The RGB switches function with reduced performance with the charge pump disabled. Charge Pump A low-noise charge pump with internal capacitors provides a doubled voltage for driving the RGB analog switches. Noise voltage from the charge pump is less than 50VP-P. The noise level is more than 80dB below the signal level, making the charge pump suitable for
9
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Complete VGA 1:2 or 2:1 Multiplexer MAX4885
standard VGA signals. The charge pump can be disabled to eliminate charge-pump noise; however, RGB switch performance is slightly degraded. Connect QP to ground for normal operation.
Table 2. HV Truth Table
EN M SEL FUNCTION 1:2 Mode Buffers Enabled H0 to H1 V0 to V1 1:2 Mode Buffers Enabled H0 to H2 V0 to V2 2:1 Mode Buffers Disabled H0 to H1 V0 to V1 2:1 Mode Buffers Disabled H0 to H2 V0 to V2 H_, V_ High Impedance
Horizontal/Vertical Sync Multiplexer
1:2 Multiplexer Mode The MAX4885 provides two modes of operation for the HSYNC and VSYNC signals. In 1:2 mode (M = 0), the HSYNC/VSYNC inputs are buffered to provide level shifting and drive capability to meet the VESA specification. 2:1 Multiplexer Mode In 2:1 mode (M = 1), the HSYNC/VSYNC output buffers are disabled, and switches pass signals directly. The HSYNC and VSYNC switches/buffers are identical, and either input can be used to route HSYNC and VSYNC signals.
0
0
0
0
0
1
0
1
0
Display Data Channel Multiplexer
The MAX4885 provides two voltage-clamped switches to route DDC signals (see Table 3). Each switch clamps signals to a diode drop less than the voltage applied on VCL. Supply +3.3V on VCL to provide voltage clamping for VESA I2C-compatible signals. If voltage clamping is not required, connect VCL to V+. The DDCA and DDCB switches are identical, and each switch can be used to route either DDC signal.
0 1 1
1
X
X
X = Don't Care
Table 3. DDC Truth Table
EN 0 0 1 SEL 0 1 X FUNCTION DDCA0 to DDCA1 DDCB0 to DDCB1 DDCA0 to DDCA2 DDCB0 to DDCB2 DDCA_, DDCB_ High Impedance
ESD Protection
As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. Additionally, the MAX4885 is protected to 8kV on RGB, HSYNC, VSYNC, and DDC switches by the Human Body Model (HBM). For optimum ESD performance, bypass each V+ pin to ground with a 0.1F or larger ceramic capacitor. Human Body Model (HBM) Several ESD testing standards exist for measuring the robustness of ESD structures. The ESD protection of the MAX4885 is characterized with the Human Body Model. Figure 5 shows the model used to simulate an ESD event resulting from contact with the human body. The model consists of a 100pF storage capacitor that is charged to a high voltage, then discharged through a 1.5k resistor. Figure 6 shows the current waveform when the storage capacitor is discharged into a low impedance.
X = Don't Care
Applications Information
1:2 Multiplexer for Low-Voltage Graphics Controllers
The MAX4885 provides the level shifting necessary to drive two standard VGA ports from a graphics controller as low as +2.2V. In 1:2 mode, internal buffers drive the HSYNC and VSYNC signals to VGA standard TTL levels. The DDC multiplexer provides level shifting by clamping signals to a diode drop less than VCL (see the Typical Operating Circuit). Connect VCL to +3.3V for normal operation, or to V+ to disable voltage clamping for DDC signals.
ESD Test Conditions
ESD performance depends on a variety of conditions. Please contact Maxim for a reliability report documenting test setup, methodology, and results.
10
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Complete VGA 1:2 or 2:1 Multiplexer MAX4885
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1500 DISCHARGE RESISTANCE DEVICE UNDER TEST
IP 100% 90% AMPERES 36.8% 10% 0 0 tRL TIME
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
Cs 100pF
STORAGE CAPACITOR
tDL CURRENT WAVEFORM
Figure 5. Human Body ESD Test Model
Figure 6. HBM Discharge Current Waveform
2:1 Multiplexer
In 2:1 mode, HSYNC and VSYNC buffers are disabled, allowing bidirectional signaling. The DDC multiplexer provides level shifting by clamping signals to a diode drop less than VCL (see the Typical Operating Circuit). Connect VCL to V+ to disable voltage clamping for DDC signals.
PC Board Layout
High-speed switches such as the MAX4885 require proper PC board layout for optimum performance. Ensure that impedance-controlled PC board traces for high-speed signals are matched in length and as short as possible. Connect the exposed pad to a solid ground plane.
Power-Supply Decoupling
Bypass each V+ pin and VCL to ground with a 0.1F or larger ceramic capacitor as close to the device as possible.
Chip Information
PROCESS: BiCMOS CONNECT EXPOSED PAD TO GND
______________________________________________________________________________________
11
Complete VGA 1:2 or 2:1 Multiplexer MAX4885
Functional Diagram
MAX4885
M
H0
*
H1 V1
V0
*
H2 V2
SEL
R0
R1
G1 G0 B1 B0 R2 QP RGB CHARGE PUMP
G2
B2 EN DDCA1 DDCA0 DDCB1 DDCB0
VCL
VOLTAGE CLAMP
DDCA2
DDCB2
12
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Complete VGA 1:2 or 2:1 Multiplexer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX4885
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
AAAAA
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
1
2
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES T1655-2 T1655-3 T1655N-1 T2055-3
D2
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3 3.00 3 3.00 3.00 3.00 3.20
E2
exceptions
L
A A1 A3 b D E e k L
MIN. NOM. MAX. MIN. NOM. MAX. 0.15
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.40 BSC. 0.50 BSC.
DOWN BONDS ALLOWED
0.25 - 0.25 - 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 L1 - 0.30 0.40 0.50 16 40 N 20 28 32 ND 4 10 5 7 8 4 10 5 7 8 NE WHHB ----WHHC WHHD-1 WHHD-2 JEDEC
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
3.00 3.00 3.00 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** **
YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES
** SEE COMMON DIMENSIONS TABLE
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
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